There is a tendency that the efficiency of access to a slave component by a master component and the throughput of data processing decrease with the increase in the number of circuit modules including a processor incorporated in a SoC for materializing a required data-processing function, a memory and a peripheral circuit. This results from the conflict between requests from master components to a slave component, and the conflict between responses by slave components to a master component, for example.
JP-A-2002-342265 discloses a computer system having the following features: first master components are assigned specialized access buses respectively; second master components are assigned access buses through an aggregate circuit which performs e.g. arbitration of access requests, provided that the number of the busses assigned to the second components is smaller than that of the second master components; and slave components can be connected through select circuits to any access buses.
JP-A-2000-200258 contains the description about a system using a crossbar-switching network which provides selectable access to internal IC nodes from outside interface pins.